1. Field of the Invention
The present invention relates generally to error correction codes and specifically to an execution unit adapted for Reed-Solomon Error Correction Code (R-S ECC) encoding and syndrome generation.
2. Background Information
Conventionally, Reed-Solomon Error Correction Code (R-S ECC) encoding and R-S ECC syndrome generation is accomplished by independent and separate circuits. For example, in Kuang Yung Liu, Architecture for VLSI Design of Reed-Solomon Decoders, IEEE Transactions on Computers, Vol. C-33, No. 2, (Febuary. 1984), the circuit illustrated is adapted for R-S ECC encoding, and the circuit shown in Kuang Yung Liu, Architecture for VLSI Design of Reed-Solomon Encoders, IEEE Transactions on Computers, Vol. C-31, No. 2, (Febuary 1982) is adapted for R-S ECC syndrome generation.
Since both R-S ECC encoding and R-S ECC syndrome generation are relatively complex operations, the hardware implementation of these operations typically requires a high number of logic circuits that occupy a correspondingly large, silicon die area. The disadvantages of providing separate circuits for encoding and for syndrome generation include the cost of the large, silicon die area as well as the high number of gates needed to implement both the circuits.
Accordingly, there is a need for an execution unit that performs both R-S ECC error encoding and R-S ECC syndrome generation while minimizing the number of transistors and logic circuits needed to implement the unit and minimizing the area this execution unit occupies on the silicon die.